This application is based upon and claims priority from prior French patent application 97 12631, filed Oct. 9, 1997, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to memory access control, and more specifically to the control of shared access to a memory by several entities that operate in an asynchronous manner.
2. Description of the Related Art
In conventional devices for application to the field of television, data to be displayed on a television screen is delivered by a screen controller that reads from a random access memory whose contents are the results of logic processing performed by a microprocessor. The clock signals that clock the screen controller and the microprocessor are fully asynchronous (in terms of frequency and phase) and each of these entities may request access to the memory at the same time. A conventional approach to shared access uses xe2x80x9cdual-accessxe2x80x9d memories in which two entities can read from or write to (simultaneously or otherwise) each of the memory locations. Such an approach to shared memory access requires the use of complex memories and can cause problems or errors in certain cases. For example, a problem situation arises when one entity requests a write to a memory location while (almost simultaneously) the other entity wishes to read from the same location.
In view of these drawbacks, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a time-shared, single-access memory, instead of a physically-shared dual-access memory. In the system, memory access requests are time-shared, and access to memory is managed by a sequencer that segments time into access windows. Each access window is reserved for one of the entities using the memory. Additionally, the sequencer is regulated by an internal clock signal of the highest priority entity. A non-priority (i.e., other or auxiliary) entity must wait for its next access window to read or store data. In this manner, control is accomplished for shared access to a memory by several peripheral entities, which are each clocked by an internal clock signal.
In a first embodiment of the present invention, the memory is a single-access, random access memory (i.e., a memory with one unique access), a priority entity is defined from among the set of peripheral entities, and the remaining entities are defined as auxiliary entities. A repetitive time frame is formulated, regulated by the internal clock signal of the priority entity, and subdivided into several groups of time windows. These groups are allocated to the peripheral entities, and each peripheral entity can access the memory only during the windows allocated to that entity.
In one preferred embodiment directed to a television application, a screen controller is the priority entity and data samplers are included among the auxiliary entities. Additionally, the auxiliary entities include a central processing unit (i.e. microprocessor) and an input/output circuit that is coupled to the memory and can store data to be written to the, memory (or to be extracted from the memory). When a memory access request signal is generated by the central processing unit during a window that is not allocated to the processing unit, the data in the input/output circuit is enabled for the next window allocated to the central processing unit; the internal operation of the central processing unit is disabled until that time.
The present invention also provides a system for controlling shared access to a random access memory. The system includes a single-access memory that is connected to a data bus and an address bus, and several peripheral entities in the form of a priority entity and auxiliary entities, each of which is clocked by an internal clock signal. Each peripheral entity can deliver a memory access request signal and includes an input/output circuit that is connected to the data bus and the address bus. Further, the input/output circuit can store data to be extracted from or written to the memory, and includes a control port for receiving at least one signal for enabling the data stored in the input/output circuit.
In one preferred embodiment, the system also includes a control interface having a sequencer that is regulated by the internal clock signal of the priority entity so as to formulate a repetitive time frame subdivided into several groups of time windows. These groups are allocated to the peripheral entities. The control interface also has a control circuit that responds to an access request signal and delivers the data enabling signal to the input/output circuit during an allocated window so as to allow access to the memory. In embodiments where one of the auxiliary entities includes a central processing unit, the control circuit also includes an inhibiting circuit. When a memory access request signal is received from the central processing unit during a window that is not allocated to that unit, the inhibiting circuit disables the internal operation of the central processing unit until the data enabling signal is received. This xe2x80x9cdisablingxe2x80x9d (or inhibiting) of the central processing unit may involve a complete interruption of the operation of the central processing unit or may merely freeze the contents of the internal registers (or flip-flops) so that there is no change in the data in these flip-flops until the disabling signal is deactivated.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.